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E2U0043-28-82
Semiconductor MSM7716
Semiconductor Single Rail Linear CODEC
This version: Aug. 1998 MSM7716 Previous version: Nov. 1996
GENERAL DESCRIPTION
The MSM7716 is a single-channel CODEC CMOS IC for voice signals that contains filters for linear A/D and D/A conversion. Designed especially for a single-power supply and low-power applications, the device is optimized for applications for the analog interfaces of audio signal processing DSPs and digital wireless systems. The analog output signal can directly drive a ceramic type handset receiver. In addition, levels for analog outputs can be set by external control.
FEATURES
* Single power supply * Low power consumption Operating mode Power down mode * Digital signal input/output interface * Sampling frequency(fs) * Transmission clock frequency * Filter characteristics : +2.7 V to +3.6 V : : : : : : 24 mW Typ. 0.05 mW Typ. 14-bit serial code in 2's complement format 4 to 16 kHz fs 14 min., 2048 kHz max. when fs = 8 kHz, complies with ITU-T Recommendation G. 714
* Built-in PLL eliminates a master clock * Two input circuits in transmit section * Two output circuits in receive section * Transmit gain adjustable using an external resistor * Receive gain adjustable by external control 8 steps, 4 dB/step * Transmit mic-amp is eliminated by the gain setting of a maximum of 36 dB. * Analog outputs can drive a load of a minimum of 1 kW ; an amplitude of a maximum of 4.0 VPP with push-pull driving. * Built-in reference voltage supply * Package options: 32-pin plastic TSOP (TSOPI32-P-814-0.50-1K) (Product name : MSM7716TS-K) 30-pin plastic SSOP (SSOP30-P-56-0.65-K) (Product name : MSM7716GS-K)
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Semiconductor
MSM7716
BLOCK DIAGRAM
MAO MAIN PBO PBIN - + SW 2 SG GEN AUTO ZERO SG PLL SYNC BCLK VR GEN RTIM - + SW 1 RC LPF 8th BPF 14 BIT ADCONV PCMOUT TCONT
SGC
VFO SW 4 AUXO - + SW 4
VOL
RC LPF
5th LPF
14 BIT DACONV PWD
RCONT PCMIN PWD logic PDN
PWI SW 3 AOUT- AOUT+ - + - + SW 3
SW CONT CONT Logic VOL CONT
DEN CDIN DCLK
VDD AG DG
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PIN CONFIGURATION (TOP VIEW)
MAIN MAO NC NC PBO PBIN NC SGC AG AUXO AOUT+ AOUT- NC NC PWI VFO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NC : No connect pin 32-Pin Plastic TSOP
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
PDN SYNC NC NC NC BCLK PCMOUT PCMIN DG DEN CDIN NC NC NC DCLK VDD
AG AUXO AOUT+ AOUT- PWI VFO NC NC NC VDD DCLK NC CDIN DEN DG
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 NC : No connect pin 30-Pin Plastic SSOP
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SGC PBIN PBO NC NC MAO MAIN NC NC PDN SYNC NC BCLK PCMOUT PCMIN
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PIN AND FUNCTIONAL DESCRIPTIONS
MAIN, MAO Transmit microphone input and the level adjustment. MAIN is connected to the noninverting input of the op-amp, and MAO is connected to the output of the op-amp. The level adjustment should be configured as shown below. During power saving and power down modes, the MAO output is in high impedance state.
C1 Microphone input R1
R2
MAO MAIN
- +
R1 : variable R2 > 20 kW C1 > 1/(2 3.14 30 R1) (F) Gain = R2/R1 < 63
SG
PBIN, PBO Transmit handset input and the level adjustment. PBIN is connected to the noninverting input of the op-amp, and PBO is connected to the output of the op-amp. The level adjustment should be configured as shown below. During power saving and power down, the PBO output is in high impedance state.
R4 Handset microphone input C2 R3
PBO PBIN
- +
R3 : variable R4 > 20 kW C2 > 1/(2 3.14 30 R3) (F) Gain = R4/R3 < 63
SG
VDD Power supply pin for +2.7 to 3.6 V (Typically 3.0 V). AG Analog signal ground. DG Ground pin for the digital signal circuits. This ground is separated from the analog signal ground in this device. The DG pin must be connected to the AG pin on the printed circuit board.
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Semiconductor VFO
MSM7716
Receive filter output. The output signal has an amplitude of 2.0 VPP above and below the signal ground voltage when the digital signal of +3 dBm0 is input to PCMIN. VFO can drive a load of 20 kW or more. This output can be externally controlled in the level range of 0 to -28 dB in 4 dB increments. During power saving or power down, VFO output is at the voltage level (VDD/2) of SG with a high impedance state. PWI, AOUT+, AOUT- PWI is connected to the inverting input of the receive driver. The receive driver output is connected to the AOUT- pin. Thus, a receive level can be adjusted with the pins PWI, AOUT-, and VFO described above. The output of AOUT+ is inverted with respect to the output of AOUT- with a gain of 1. The output signal amplitudes are a maximum of 2.0 VPP. These outputs, above and below the signal ground voltage (VDD/2), can drive a load of a minimum of 1 kW with push-pull driving (a load connected between AOUT+ and AOUT-). The output amplitudes are 4 VPP maximum during push-pull driving. These outputs can be mute controlled externally. These outputs are operational during power saving and output the SG voltage (VDD/2) in the high impedance state. AUXO Auxiliary receive filter output. The output signal is inverted with respect to the VFO output with a gain of 1. The output signal swings above and below the SG voltage (VDD/2), and can drive a minimum load of 0.5 kW with respect to the SG voltage. The output can be mute controlled externally. During power saving and power down, AUXO outputs the SG voltage (VDD/2) in the high impedance state. BCLK Shift clock signal input for PCMIN and PCMOUT. The frequency is equal to the data rate. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power-saving state.
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Semiconductor SYNC
MSM7716
Synchronizing signal input. In the transmit section, the PCM output signal from the PCMOUT pin is output synchronously with this synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing signals of the transmit section. In the receive section, 14 bits required are selected from serial input of PCM signals on the PCMIN pin by the synchronizing signal. Signals in the receive section are synchronized by this synchronizing signal. This signal must be synchronized in phase with the BCLK. When this signal frequency is 8 kHz, the transmit and receive section have the frequency characteristics specified by ITU-T G. 714. The frequency characteristics for 8 kHz are specified in this data sheet. For different frequencies of the SYNC signal, the frequency values in this data sheet should be translated according to the following equation: Frequency values described in the data sheet the SYNC frequency values to be actually used 8 kHz Setting this signal to logic "1" or "0" drives the device to power-saving state. PCMIN PCM signal input. A serial PCM signal input to this pin is converted to an analog signal synchronously with the SYNC signal and BCLK signal. The data rate of the PCM signal is equal to the frequency of the BCLK signal. The PCM signal is shifted at a falling edge of the BCLK signal. The PCM signal is latched into the internal register when shifted by 14 bits. The top of the data (MSD) is identified at the rising edge of SYNC. The input signal should be input in the 14-bit 2's complement format. The MSD bit represents the polarity of the signal with respect to the signal ground.
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Semiconductor PCMOUT
MSM7716
PCM signal output. The PCM output signal is output from MSD in sequential order, synchronously with the rising edge of the BCLK signal. MSD may be output at the rising edge of the SYNC signal, depending on the timing between BCLK and SYNC. This pin is in high impedance state except during 14-bit PCM output. It is also high impedance during power saving or power down mode. A pull-up resistor must be connected to this pin, because its output is configured as an open drain. The output coding format is in 14-bit 2's complement. The MSD represents a polarity of the signal with respect to the signal ground. Table 1
Input/Output Level MSD +Full scale +1 0 -1 -Full scale 0 0 0 1 1 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 1 0 1 0 PCMIN/PCMOUT
PDN Power down control signal input. A digital "L" level drives both transmit and receive circuits to a power down state. The control registers are set to the initial state. SGC Connection of a bypass capacitor for generating the signal ground voltage level. Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and the SGC pin.
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DEN, DCLK, CDIN Serial control ports for the microcontroller interface. Writing data to the 8-bit control register enables control of the receive output level and the signal path. DEN is the "Enable" signal pin, DCLK is the data shift clock input pin, and CDIN is the control data input pin. When powered down (PDN = 0), the initial values are set as shown in Tables 2, 3, and 4. The initial values are held unless the control data is written after power-down release. The control data is shifted at the rising edge of the DCLK signal and latched into the internal control register at the rising edge of the DEN signal. When the microcontroller interface is not used, these pins should be connected to DG. The bit map of the 8-bit control register is shown below.
B7 SW1 B6 SW2 B5 SW3 B4 SW4 B3 -- B2 VOL1 B1 VOL2 B0 VOL3
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ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Analog Input Voltage Digital Input Voltage Storage Temperature Symbol VDD VAIN VDIN TSTG Condition
AG = DG = 0 V AG = DG = 0 V AG = DG = 0 V --
Rating -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -55 to +150
Unit V V V C
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Operating Temperature Analog Input Voltage High Level Input Voltage Low Level Input Voltage Symbol VDD Ta VAIN VIH VIL Gain = 1 SYNC, BCLK, PCMIN, PDN, DEN, DCLK, CDIN Condition -- -- Min. 2.7 -30 -- 0.45 VDD 0 Typ. 3.0 +25 -- -- -- Max. 3.6 +85 1.4 VDD 0.16 VDD 128 Fs 16 60 50 50 -- -- -- -- -- -- -- 100 -- -- -- -- -- -- -- -- +100 +10 1000 Unit V C VPP V V
Clock Frequency Sync Pulse Frequency Clock Duty Ratio Digital Input Rise Time Digital Input Fall Time Sync Pulse Setting Time High Level Sync Pulse Width *1 Low Level Sync Pulse Width *1 PCMIN Setup Time PCMIN Hold Time Digital Output Load DCLK Pulse Width DEN Setting Time 1 DEN Setting Time 2 CDIN Setup Time CDIN Hold Time Analog Input Allowable DC Offset Allowable Jitter Width
FC FS DC tIr tIf
BCLK SYNC BCLK SYNC, BCLK, PCMIN, PDN, DEN, DCLK, CDIN
14 Fs 4.0 40 -- -- 100 100 1 BCLK 1 BCLK 100 100 0.5 -- 50 50 50 50 50 50 50 50 -100 -10 -- --
-- 8.0 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
kHz kHz % ns ns ns ns -- -- ns ns kW pF ns ns ns ns mV mV ns
tXS, tRS BCLKAESYNC, See Fig.1 tSX, tSR SYNCAEBCLK, See Fig.1 tWSH tWSL tDS tDH RDL CDL tWCL tWCH tCDL tDCL tCDH tDCH tCDS tCDH Voff -- SYNC, See Fig.1 SYNC, See Fig.1 Refer to Fig.1 Refer to Fig.1 Pull-up resistor DCLK Low width, See Fig.2 DCLK High width, See Fig.2 DCLKAEDEN, See Fig.2 DENAEDCLK, See Fig.2 DCLKAEDEN, See Fig.2 DENAEDCLK, See Fig.2 See Fig.2 See Fig.2 Transmit gain stage, Gain = 0 dB Transmit gain stage, Gain = 20 dB SYNC, BCLK
*1 For example, the minimum pulse width of SYNC is 488 ns when the frequency of BCLK is 2048 kHz. 9/22
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MSM7716
RECOMMENDED OPERATING CONDITIONS (Continued)
Parameter Symbol tSD Digital Output Delay Time tXD1 tXD2 tXD3 CL = 50 pF + 1 LSTTL Pull-up resistor = 500 W Condition Min. 20 20 20 20 Typ. -- -- -- -- Max. 100 100 100 100 ns Unit
ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
Parameter Symbol IDD1 Power Supply Current IDD2 IDD3 High Level Input Voltage Low Level Input Voltage High Level Input Leakage Current Low Level Input Leakage Current Digital Output Low Voltage Digital Output Leakage Current Input Capacitance VIH VIL IIH IIL VOL IO CIN (Fs = 8 kHz, VDD = 2.7 V to 3.6 V, Ta = -30C to +85C) Condition
Operating mode, VDD = 3.6 V No signal VDD = 3.0 V
Min. -- -- -- -- 0.45
Typ. 10.0 8.0 6.0 0.01 -- -- -- -- 0.2 -- 5
Max. 17.0 13.0 11.0 0.05 VDD 0.16 VDD 2.0 0.5 0.4 10 --
Unit mA mA mA mA V V mA mA V mA pF
Power-saving mode, PDN = 1, SYNC, BCLK AE OFF Power-down mode, PDN = 0
SYNC, BCLK, PCMIN, DEN, CDIN, DCLK, PDN -- --
PCMOUT pull-up resistor = 500 W
VDD 0.0 -- -- 0.0 -- --
-- --
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Semiconductor Transmit Analog Interface Characteristics
Parameter Input Resistance Output Load Resistance Output Load Capacitance Output Amplitude Offset Voltage Symbol RINX RLGX CLGX VOGX VOSGX Gain = 1 MAIN, PBIN MAO, PBO with respect to SG
MSM7716
(Fs = 8 kHz, VDD = 2.7 V to 3.6 V, Ta = -30C to +85C) Min. 10 20 -- -0.7 -20 Typ. -- -- -- -- -- Max. -- -- 30 +0.7 +20 Unit MW kW pF V mV
Condition
Receive Analog Interface Characteristics
Parameter Output Resistance Symbol ROVO VFO RLAO RLVO Output Load Capacitance Output Amplitude Offset Voltage CLAO VOAO VOSA
(Fs = 8 kHz, VDD = 2.7 V to 3.6 V, Ta = -30C to +85C) Condition Min. -- -- 0.5 20 -- -1.0 -100 Typ. -- -- -- -- -- -- -- Max. 10 100 -- -- 50 +1.0 +100 Unit W W kW kW pF V mV
ROAO AUXO, AOUT+, AOUTAUXO, AOUT+, AOUT- (each) with respect to SG VFO with respect to SG Output open AUXO, AOUT+, AOUT-, VFO with respect to SG AUXO, AOUT+, AOUT-, VFO with respect to SG
Output Load Resistance
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Semiconductor AC Characteristics
Parameter Symbol Loss 1 Loss 2 Overall Frequency Response Loss 3 Loss 4 Loss 5 Loss 6 Loss T1 Loss T2 Transmit Frequency Response (Expected Value) Loss T3 Loss T4 Loss T5 Loss T6 Loss R1 Receive Frequency Response (Expected Value) Loss R2 Loss R3 Loss R4 Loss R5 SD 1 SD 2 SD 3 Overall Signal to Distortion Ratio SD 4 SD 5 SD 6 SD 7 SD T1 SD T2 Transmit Signal to Distortion Ratio (Expected Value) SD T3 SD T4 SD T5 SD T6 SD T7 SD R1 SD R2 Receive Signal to Distortion Ratio (Expected Value) SD R3 SD R4 SD R5 SD R6 SD R7 1020 1020 1020 Freq. (Hz) 60 300 1020 2020 3000 3400 60 300 1020 2020 3000 3400 300 1020 2020 3000 3400 3 0 -10 -20 -30 -40 -50 3 0 -10 -20 -30 -40 -50 3 0 -10 -20 -30 -40 -50 *1 *1 Analog to Analog *1 0 -0.15 -0.15 0.0 55.9 55.9 55.9 45.9 35.9 25.9 15.9 58 58 58 48 38 28 18 58 58 58 48 38 28 18 0 0
MSM7716
(Fs = 8 kHz, VDD = 2.7 V to 3.6 V, Ta = -30C to +85C) Level Condition (dBm0) Min. 20 Analog to Analog -0.2 -0.2 -0.2 0 20 -0.15 -0.15 -0.15 0 -0.15 Typ. -- -- Reference -- -- -- -- -- Reference -- -- -- -- Reference -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- +0.2 +0.2 0.8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- dB dB dB dB +0.2 +0.2 0.8 +0.2 +0.4 +0.4 1.6 -- +0.2 dB Max. -- +0.4 dB Unit
*1
Psophometric filter is used.
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Semiconductor AC Characteristics (Continued)
Parameter Symbol GT 1 GT 2 Overall Gain Tracking GT 3 GT 4 GT 5 GT T1 Transmit Gain Tracking (Expected Value) GT T2 GT T3 GT T4 GT T5 GT R1 Receive Gain Tracking (Expected Value) GT R2 GT R3 GT R4 GT R5 1020 1020 1020 Freq. (Hz)
MSM7716
(Fs = 8 kHz, VDD = 2.7 V to 3.6 V, Ta = -30C to +85C) Level Condition (dBm0) 3 Analog -10 -40 -50 -55 3 -10 -40 -50 -55 3 -10 -40 -50 -55 -0.3 -0.6 -1.2 -0.3 -0.6 -1.2 -0.3 to Analog -0.3 -1.3 -1.6 -0.3 Min. -0.4 Typ. +0.01 Reference 0.00 -0.03 -0.15 +0.01 Reference 0.00 -0.03 +0.15 -0.06 Reference -0.02 -0.02 -0.27 +0.3 +0.6 +1.2 dB +0.3 +0.6 +1.2 +0.3 dB +0.8 +1.3 +1.6 +0.3 dB Max. +0.4 Unit
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Semiconductor AC Characteristics (Continued)
Parameter Overall Idle Channel Noise Transmit Idle Channel Noise (Expected Value) Receive Idle Channel Noise (Expected Value) Absolute Level (Initial Level) AV R Absolute Level (Deviation of Temperature and Power) AV Tt AV Rt to 3.6 V Ta = -30 to 85C A to A Absolute Delay tD tGD T1 Transmit Group Delay tGD T3 Receive Group Delay Crosstalk Attenuation tGD R2 CR T CR R 1020 500 0 *3 2800 2800 1020 0 0 *3
TRANS AE RECV RECV AE TRANS
MSM7716
(Fs = 8 kHz, VDD = 2.7 V to 3.6 V, Ta = -30C to +85C) Freq. (Hz) -- -- -- Level Condition (dBm0) AIN: no signal -- *1 -- -- AIN: no signal *1 VDD = 3.0 V 1020 0 Ta = 25C *2 VDD = +2.7 0.483 -0.2 -0.2 0.500 -- -- 0.518 +0.2 +0.2 dB dB Min. -- -- -- 0.338 Typ. -70 -76 -76 0.350 Max. -66 -74 dBmOp -74 0.362 Vrms Unit dBmOp
Symbol Nidle A Nidle T Nidle R AV T
0
BCLK = 64 kHz
-- -- -- -- -- -- 75 70
-- -- -- -- 0.00 0.12 85 80
0.6 0.325 0.175 0.325 0.125 0.325 -- --
ms
tGD T2 600 to 2600 tGD R1 500 to 2600
ms
ms dB
*1 *2
*3
Psophometric filter is used. AVT is defined at MAO and PBO-PCMOUT. AVR is defined at PCMIN-VFO. VOL = 0 dB Minimum value of the group delay distortion
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Semiconductor AC Characteristics (Continued)
Parameter Discrimination Out-of-band Spurious Intermodulation Distortion Power Supply Noise Rejection Ratio Auxiliary Output Gain Symbol
MSM7716
(Fs = 8 kHz, VDD = 2.7 V to 3.6 V, Ta = -30C to +85C) Min. 30 -- -- -- -1.0 -5 -9 -13 -17 -21 -25 -29 Typ. 32 -37.5 -52 30 0 -4 -8 -12 -16 -20 -24 -28 Max. -- -35 -40 -- +1.0 -3 -7 -11 -15 -19 -23 -27 dB Unit dB dBm0 dBm0 dB dB
Freq. Level Condition (Hz) (dBm0) 0 to 4.6 kHz to 0 DIS 4000 Hz 72 kHz S 300 to 3400 fa = 470 fb = 320 0 to 50 kHz 1020 0 -4 50 mVPP 0 4.6 kHz to 100 kHz 2fa - fb *1 VFO to AUXO Set at - 4 dB -8 dB -12 dB 1020 0 Referenced to 0 dB setting -16 dB -20 dB -24 dB -28 dB
IMD PSR T PSR R GAUX GV2 GV3 GV4
VOL Gain Setting Value
GV5 GV6 GV7 GV8
*1
Measured inband.
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Semiconductor
TIMING DIAGRAM
PCM Data Output Timing
Transmit Timing BCLK tXS SYNC
tXD1 PCMOUT
Receive Timing BCLK tRS SYNC
PCMIN
MCU Interface Timing
DCLK
tCDL DEN
CDIN
, , ,,
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tSX tWSL tWSH tSD MSD D2 D3 D4 tXD2 D5 D6 D7 D8 D9 tXD3 D10 D11 D12 D13 D14 When tXS 1/2 * Fc, the Delay of the MSD bit is defined as tXD1. When tSX < 1/2 * Fc, the Delay of the MSD bit is defined as tSD. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tSR tWSL tWSH MSD D2 D3 tDS D4 D5 tDH D6 D7 D8 D9 D10 D11 D12 D13 D14
MSM7716
16
17
16
17
Figure 1 Basic Timing Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
tDCL
tWCL tWCH
tCDH
tDCH
tCDS
tCDH
B7
B6
B5
B4
B3
B2
B1
B0
Figure 2 MCU Interface Timing Diagram
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FUNCTIONAL DESCRIPTION
Control Data Description SW1, SW2 - - Control bits for the transmit speech path switch. The AD converter input is selected according to the bit data shown in Table 2. Table 2
State T1 T2 T3 T4 SW2 0 0 1 1 SW1 0 1 0 1 AD Converter Input No signal (muting state) Input signal to MAIN Input signal to PBIN Addition signal of both MAIN and PBIN Remarks -- At initial setting -- The gain of each input drops about 6 dB
SW3, SW4 - - Control bits for the receive speech path switch. The control should be performed according to Table 3. Table 3
State R1 R2 R3 R4 SW4 0 0 1 1 SW3 0 1 0 1 AOUT+, AOUT- Output SG PWI SG PWI SG: signal ground voltage. AUXO Output SG SG DA DA Remarks -- At initial setting -- --
DA: DA converter output.
VOL1, VOL2, VOL3 - - - Control bits for the receive signal output level. By controlling these bits, the output levels of VFO and AUXO can be controlled according to Table 4. Table 4
VOL1 0 0 0 0 1 1 1 1 VOL2 0 0 1 1 0 0 1 1 VOL3 0 1 0 1 0 1 0 1 Receive Signal Gain 0 dB -4 dB -8 dB -12 dB -16 dB -20 dB -24 dB -28 dB Remarks At initial setting -- -- -- -- -- -- --
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MSM7716
APPLICATION CIRCUIT
1 kW MSM7716 Microphone analog input Handset analog input Addition signal input MAIN 1 mF 20 kW 20 kW MAO 20 kW 20 kW PBIN PBO VFO PWI PDN Power down control input "1" = Operation "0" = Power down PCMIN BCLK SYNC PCM input PCM shift clock input 8 kHz SYNC pulse input PCMOUT PCM output +3 V
1 mF
1 mF
20 kW
20 kW 20 kW
Analog output* Analog inverted output* Auxiliary output* 0.1 mF
AOUT- AOUT+ AUXO SGC AG DCLK DEN CDIN Controller
0V +3 V 10 mF 0 to 10 W + 1 mF
DG VDD
* The swing of the analog output signal is a maximum of 1.0 V above and below the VDD/2 offset level.
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MSM7716
APPLICATION INFORMATION
Digital pattern for 0 dBm0 The digital pattern for 0 dBm0 is shown below. (SYNC frequency = 8 kHz, signal frequency = 1 kHz)
S2
S3
S1
S4
SG
S5
S8
S6 Sample No. MSD D2 S1 S2 S3 S4 S5 S6 S7 S8 0 0 0 0 1 1 1 1 0 1 1 0 1 0 0 1 D3 1 0 0 1 0 1 1 0 D4 D5 0 1 1 0 1 0 0 1 0 0 0 0 1 1 1 1 D6 0 0 0 0 1 1 1 1 D7 1 1 1 1 0 0 0 0
S7
D8 D9 D10 D11 D12 D13 D14 0 1 1 0 1 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 0 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 0 1 1 0
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NOTES ON USE
* To ensure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins. * Connect the AG pin and the DG pin as close as possible. Connect to the system ground with low impedance. * Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If the use of IC socket is unavoidable, use the short lead type socket. * When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave sources such as power supply transformers surround the device. * Keep the voltage on the VDD pin not lower than -0.3 V even instantaneously to avoid latchup that may otherwise occur when power is turned on. * Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid erroneous operation and the degradation of the characteristics of these devices.
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MSM7716
PACKAGE DIMENSIONS
(Unit : mm)
TSOPI32-P-814-0.50-1K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.27 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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Semiconductor
MSM7716
(Unit : mm)
SSOP30-P-56-0.65-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.19 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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